With advanced designs of digital integrated circuits, standard cell design libraries are also constantly progressing. Manufacturing processes in nanotechnology encounter many manufacturability problems, and design processes of integrated circuits also encounter multiple problems, which ultimately affect the yield of integrated circuits. In general, a standard-cell based design is implemented using a set of predefined logic cells referred to as standard cells. The set of standard cells is referred to as a standard cell library. A standard cell library may contain the following components: layout of the cells, Verilog models or VHDL models, parasitic extraction models, DRC rule decks. Each standard cell has a unique logic function (e.g., a D-flipflop, a NAND gate, a NOR gate, etc.). In a standard-cell based design, a standard cell may be instantiated multiple times and an integrated circuit design is implemented by using a placement and routing tool to place all instantiated standard cells and interconnect (routing) them. Thus, optimizing the manufacturability of a standard cell library is a critical step to improve the design flow of integrated circuits.
In conventional physical implementation flows of standard-cell based designs, an engineer can only perform a lithography verification simulation of a standard-cell based design, but cannot predict lithography hot spots after the standard-cell based design has been physically implemented. In a physical implementation, a router may add one or more vias to a standard cell pin to connect the standard cell, which may create hard-to-solve lithography hot spots. A layout engineer is required to spend significant time and effort to resolve hot spots that occur on the pin connections of the standard cell.